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可配置电阻分压型DAC-PUF电路设计
引用本文:汪鹏君,李刚,钱浩宇.可配置电阻分压型DAC-PUF电路设计[J].电子学报,2016,44(7):1630-1635.
作者姓名:汪鹏君  李刚  钱浩宇
作者单位:宁波大学电路与系统研究所, 浙江宁波 315211
基金项目:国家自然科学基金(No.61474068,No.61274132);浙江省自然科学基金(No.LQ14F040001);浙江省教育厅项目(Y201430798)
摘    要:物理不可克隆函数(Physical Unclonable Function,PUF)电路利用结构和设计参数相同的单元电路在制造过程中存在的随机工艺偏差,产生具有唯一性、随机性和不可克隆性的密钥.通过对电阻失配和数模转换器(Digital to Analogue Conversion,DAC)的研究,提出一种可配置电阻分压型DAC-PUF电路设计方案.该PUF电路由输入寄存器、电阻分压型DAC、电压比较器和时序控制模块构成.通过激励信号配置DAC单元,使该PUF电路无需更换硬件便可实现输出密钥的变化.在TSMC-LP 65nm CMOS工艺下采用全定制方式进行版图设计,面积为72.4μm×87.8μm.实验结果表明该PUF电路唯一性高,且在不同温度(-40~125℃)和电压(1.08~1.32V)下随机性和可靠性分别大于99.1%和97.8%,可广泛应用于信息安全领域.

关 键 词:物理不可克隆函数  数模转换器  可配置  电路设计  
收稿时间:2015-11-19

Design of Configurable Resistance Divider Type DAC-PUF Circuit
WANG Peng-jun,LI Gang,QIAN Hao-yu.Design of Configurable Resistance Divider Type DAC-PUF Circuit[J].Acta Electronica Sinica,2016,44(7):1630-1635.
Authors:WANG Peng-jun  LI Gang  QIAN Hao-yu
Affiliation:Institute of Circuits and Systems, Ningbo University, Ningbo, Zhejiang 315211, China
Abstract:Physical Unclonable Functions (PUF)exploits process variation across same structure and design parameter unit circuits during the manufacturing processes to generate numerous unique,random and unclonable security keys.In this pa-per,a configurable resistance divider type DAC-PUF scheme is proposed,which consists of input register,resistor-string based DAC,voltage comparator and timing control module.After configuring the DAC cell by applying input challenges,the PUF circuit updates keys without physically replacement.In TSMC-LP 65 nm CMOS technology,the layout occupies 72. 4μm × 87. 8μm with custom designing.Experimental results show that the PUF circuit possesses nice statistical characteristic of u-niqueness,high randomness of 99. 1%and high stability of 97. 8%,both with respect to supply voltage variation from 1. 08V to 1. 32V,and temperature variation from -40℃to 125℃.It can be effectively used in information security field.
Keywords:physical unclonable function  digital to analogue conversion  configurable  circuit design
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