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Low Voltage High-Speed CMOS Square-Law Composite Transistor Cell |
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| Authors: | Changku Hwang Akira Hyogo Hong-sun Kim Mohammed Ismail Keitaro Sekine |
| Affiliation: | (1) Research & Development Division, Hitachi America, Ltd., San Jose, CA 95134–1626, USA;(2) Department of Electrical Engineering, Faculty of Science and Technology, Science University of Tokyo, Noda-shi, 278–8510, Japan;(3) Solid-State Microelectronics Laboratory, Department of Electrical Engineering, The Ohio State University, Columbus, OH 43210, USA |
| Abstract: | A new low voltage high-speed CMOS composite transistor is presented. It lowers supply voltage down to |Vt|+2 Vds,sat and considerably extends input voltage operating range and achieves high speed operation. As an application example, it is used in the design of a high-speed four quadrant analog multiplier. Simulations results using MOSIS 2  m N-well process with a 3 V supply are given. |
| Keywords: | analog signal processing CMOS low voltage composite transistor multiplier |
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