Advanced HiCTE flip chip packaging of 90-nm Cu/Low-K chips: Underfill,novel terminal pad structures,and processing optimization

Packaging of 90-nm Cu/Low-K chips presents a serious challenge, which requires an advanced ceramic flip chip solution. Finer Cu interconnects are expected to interact differently with the current underfill-to-die passivation stack-up structures used for Al or previous Cu technology nodes especially in system level applications. Furthermore, the more porous and brittle-proned advanced Low-K (K<3) dielectrics present additional process incompatibility problems such as stress-induced crackings and delaminations. These reliability issues in various stress-relieving passivation structures and materials (i.e., Benzocyclobutene (BCB) and single versus double SiOxNy passivations) have not been extensively studied. This study analyzes the effect of the eight metal layer 90-nm Cu/Low-K flip chip devices through designed experiments using two relatively different underfill materials, standard terminal pad and novel passivation structures, and JEDEC Level-3 reliability stressings: temperature cycling (TC), highly accelerated stress testing (HAST), and high-temperature storage (HTS). Black Diamond Low-K and HiCTE ceramic substrates are employed for the large package form factor. The active Si uses eutectic stencil-pasted SnPb bump and BGA balls with Ti/Ni-V/Al-Cu reflectory thin film-deposited under bump metallurgy (UBM). It is found that the double passivation pad structures are less susceptible to reliability damage for various types of underfills, although a single passivation with BCB coating combined with an optimal underfill can also yield a similar favorable result. The metallurgical effect of delamination cracking, HiCTE flip chip and stress-relieving passivation structures, and the underfill interface failure mode mechanism are examined by functional testing, chemical deprocessings, scanning acoustic microscope (SAM), and scanning electron microscope (SEM)/energy-dispersive x-ray (EDX). The presented results are significant for the development of flip chip packaging technologies for future advanced Cu/Low-K generations.