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抗辐射128kb PDSOI静态随机存储器
引用本文:赵凯,刘忠立,于芳,高见头,肖志强,洪根深. 抗辐射128kb PDSOI静态随机存储器[J]. 半导体学报, 2007, 28(7): 1139-1143
作者姓名:赵凯  刘忠立  于芳  高见头  肖志强  洪根深
作者单位:中国科学院半导体研究所,北京 100083; 传感器技术国家重点实验室,北京 100083;中国科学院半导体研究所,北京 100083; 传感器技术国家重点实验室,北京 100083;中国科学院半导体研究所,北京 100083; 传感器技术国家重点实验室,北京 100083;中国科学院半导体研究所,北京 100083; 传感器技术国家重点实验室,北京 100083;中国电子科技集团第58研究所,无锡 214035;中国电子科技集团第58研究所,无锡 214035
摘    要:介绍在部分耗尽绝缘体上硅(PD SOI)衬底上形成的抗辐射128kb静态随机存储器.在设计过程中,利用SOI器件所具有的特性,对电路进行精心的设计和层次化版图绘制,通过对关键路径和版图后全芯片的仿真,使得芯片一次流片成功.基于部分耗尽SOI材料本身所具有的抗辐射特性,通过采用存储单元完全体接触技术和H型栅晶体管技术,不仅降低了芯片的功耗,而且提高了芯片的总体抗辐射水平.经过测试,芯片的动态工作电流典型值为20mA@10MHz,抗总剂量率水平达到500krad(Si),瞬态剂量率水平超过2.45×1011 rad(Si)/s.这些设计实践必将进一步推动PD SOI CMOS工艺的研发,并为更大规模抗辐射电路的加固设计提供更多经验.

关 键 词:部分耗尽绝缘体上硅  静态随机存储器  加固设计
文章编号:0253-4177(2007)07-1139-05
修稿时间:2007-03-05

Radiation-Hardened 128kb PDSOI CMOS Static RAM
Zhao Kai,Liu Zhongli,Yu Fang,Gao Jiantou,Xiao Zhiqiang and Hong Genshen. Radiation-Hardened 128kb PDSOI CMOS Static RAM[J]. Chinese Journal of Semiconductors, 2007, 28(7): 1139-1143
Authors:Zhao Kai  Liu Zhongli  Yu Fang  Gao Jiantou  Xiao Zhiqiang  Hong Genshen
Affiliation:Integrated Technology Center,Institute of Semiconductors,Chinese Academy of Sciences,Beijing 100083,China; State Key Laboratories of Transducer Technology,Beijing 100083,China;Integrated Technology Center,Institute of Semiconductors,Chinese Academy of Sciences,Beijing 100083,China; State Key Laboratories of Transducer Technology,Beijing 100083,China;Integrated Technology Center,Institute of Semiconductors,Chinese Academy of Sciences,Beijing 100083,China; State Key Laboratories of Transducer Technology,Beijing 100083,China;Integrated Technology Center,Institute of Semiconductors,Chinese Academy of Sciences,Beijing 100083,China; State Key Laboratories of Transducer Technology,Beijing 100083,China;The 58th Institute,CETC,Wuxi 214035,China;The 58th Institute,CETC,Wuxi 214035,China
Abstract:A radiation-hardened 128kbit asynchronous SRAM fabricated in partial depletion silicon on insulator substrate is presented.Special characteristics of SOI devices are used in the design process.After careful circuit design,hierarchical layout design,and simulation of critical path,the SRAM chip was fabricated in the first turn-out.Besides the radiation-hardened characteristics of SOI material,fully-body-tied 6T memory cell and H-type gate MOSFETs techniques are also implemented in this PDSOI SRAM.These advanced techniques reduce the power consumption and raise the radiation-hardened level of this SRAM.The final testing shows that the 128k bit SOI SRAM has a typical operating current of 20mA at 10MHz,total dose tolerance of 500krad(Si),and dose rate survivability of 2.45e11rad (Si)/s.The implementation of radiation-hardened 128k SOI SRAM will accelerate the development of PD SOI CMOS processes,and will surely contribute more to the radiation design of VLSI circuits in the future.
Keywords:partial-depletion SOI  static RAM  radiation hardened design
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