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SrO capping effect for La2O3/Ce-silicate gate dielectrics |
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| Authors: | K Kakushima K Okamoto M Kouda T Kawanago P Ahmet K Tsutsui T Hattori |
| Affiliation: | a Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology, 4259 Nagatsuta, Midori-ku, Yokohama 226-8502, Japan b Frontier Research Center, Tokyo Institute of Technology, 4259 Nagatsuta, Midori-ku, Yokohama 226-8502, Japan c Department of Electrical and Electronic Engineering, Tokyo City University, 1-28-1 Tamazutsumi, Setagaya-ku, Tokyo 158-8557, Japan |
| Abstract: | The chemical bonding states and electrical characteristics of SrO capped La2O3/CeOx gate dielectric have been examined. Angle-resolved X-ray photoelectron spectroscopy measurement has revealed that Sr atoms diffuse into silicate layer to form SrLa-silicate after annealing. Owing to the incorporation of Sr atoms into silicate layer, a transistor operation with an equivalent oxide thickness (EOT) below 0.5 nm has been demonstrated. A strongly degraded effective electron mobility of 78 cm2/V s at 1 MV/cm has been obtained, which fit well with the general trend in small EOT range below 1 nm. Although process optimization is needed to improve the performance of transistors, Sr capping technique can be useful for EOT scaling. |
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