A fully integrated CMOS voltage regulator for supply-noise-insensitive charge pump PLL design |
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Authors: | Quan Sun Youguang Zhang Kimmo Jaaskelainen |
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Affiliation: | a School of Electronic and Information Engineering, Beihang University, 100191 Beijing, China b Institut Pluridisciplinaire Hubert-Curien, UMR 7178 CNRS/ULP, 23, rue du Loess, 67037 Strasbourg Cedex, France |
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Abstract: | In this paper, a new design of on-chip CMOS voltage regulator, which provides two stable power supplies to charge pump and voltage controlled oscillator (VCO) in charge pump phase-locked loop (PLL), is presented. A power supply noise rejection (PSNR) whose peaking is less than −40 dB is achieved over the entire frequency spectrum for VCO supply. The voltage regulator provides maximum 14 mA current, and static current is about 780 μA at 3.3 V. Based on the proposed voltage regulator, a PLL clock generator has been developed and measured in the AMS 0.35 μm CMOS process. Operating at 160 MHz, a period jitter of 13.64 ps was measured under a clean power supply, while period jitter became 16.24 ps under a power supply modulated with a 400 mV, 10 kHz square wave. |
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Keywords: | Jitter PLL Power supply noise Voltage regulators |
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