Design, assembly and reliability of large die and fine-pitch Cu/low-k flip chip package |
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Authors: | Yue Ying Ong Soon Wee Ho Vasarla Nagendra Sekhar Samuel Lim Yak Long Leong Ching Wai Jimmy Ong Xiaowu Zhang John H. Lau David Yeo Zhang Yanfeng Dong Kyun Sohn |
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Affiliation: | a Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), 11 Science Park Road, Singapore Science Park II, Singapore 117685, Singapore b National University of Singapore, Department of Mechanical Engineering, 9 Engineering Drive 1, Singapore 117575, Singapore c Nanyang Technological University, School of Materials Science and Engineering, Nanyang Avenue, Singapore 639798, Singapore d Chartered Semiconductor Manufacturing Ltd., 60 Woodlands Industrial Park D Street 2, Singapore 738406, Singapore |
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Abstract: | This paper reports the design, assembly and reliability assessment of 21 × 21 mm2 Cu/low-k flip chip (65 nm node) with 150 μm bump pitch and high bump density. To reduce the stress from the solder bump pad to low-k layers, Metal Redistribution Layer (RDL) and Polymer Encapsulated Dicing Lane (PEDL) are applied to the Cu/low-k wafer. Lead-free Sn2.5Ag, high-lead Pb5Sn and Cu-post/Sn37Pb bumps are evaluated as the first-level interconnects. It is found that the flip chip assembly of high-lead bumped test vehicle requires the right choice of flux and good alignment between the high-lead solder bumps and substrate pre-solder alloy to ensure proper solder bump and substrate pre-solder alloy wetting. Joint Electron Device Engineering Council (JEDEC) standard reliability is performed on the test vehicle with different first-level interconnects, underfill materials and PEDL.By integrating PEDL to the Cu/low-k chip, the reliability performance of the flip chip package has been improved by almost two times. This paper has demonstrated Moisture Sensitivity Test-Level 2 (MST-L2) qualified large die and fine-pitch Cu/low-k flip chip package. The presented results are significant for the development of flip chip packaging technologies for future advanced Cu/low-k generations. |
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