Using age registers for a simple load–store queue filtering |
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Authors: | F Castro D Chaver L Pinuel M Prieto F Tirado |
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Affiliation: | ArTeCS Group, University Complutense of Madrid, Spain |
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Abstract: | One of the main challenges of modern processor design is the implementation of a scalable and efficient mechanism to detect memory access order violations as a result of out-of-order execution. Traditional age-ordered associative load and store queues are complex, inefficient, and power-hungry. In this paper, we introduce two new LSQ filtering mechanisms with different design tradeoffs, but both explicitly rely on timing information as a primary instrument to rule out dependence violation and enforce memory dependences. Our timing-centric design operates at a fraction of the energy cost of an associative LQ and SQ with no performance degradation. |
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