SRAM灵敏放大器的设计改进及其Hspice仿真分析

静态随机存取存储器（SRAM）由于其自身的低功耗和高速的优势而成为半导体存储器中不可或缺的重要产品。提高和改善静态存储器的性能依然是集成电路设计领域的重要课题。从降低静态存储器功耗的角度出发，重点研究了静态存储器的关键模块——灵敏放大器的工作机理和结构，设计了一种改进型的锁存型灵敏放大器，Hspice的仿真表明，该放大器的功耗大大低于传统的静态存储器的灵敏放大器模块的功耗。

Design of sensitive amplifier for SRAM memory and its simulation based on Hspice

Static random access memory(SRAM) has become an indispensable member of semiconductor memory family due to its low power consumption and high-speed performance.It is still an important researching topic in IC design field to raise and to improve SRAM performance.For the purpose to reduce the SRAM power dissipation,and based on the study of the working mechanisms and the structure of sensitive amplifier used as the key module of SRAM,this article proposes and implementes an improved Latch-style sensitive amplifier,the Hspice simulation indicates that its power dissipation is much lower than that of the traditional sensitive amplifier used in SRAM.