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Computational modelling for reliable flip-chip packaging at sub-100 μm pitch using isotropic conductive adhesives
Authors:S Stoyanov  R Kay  C Bailey  M Desmulliez  
Affiliation:aCentre for Numerical Modelling and Process Analysis, University of Greenwich, 30 Park Row, Greenwich, London SE10 9LS, UK;bMicroStencil Limited, Earl Mountbatten Building, Edinburgh EH14 4AS, UK;cHeriot-Watt University, MicroSystems Engineering Centre, Edinburgh EH14 4AS, UK
Abstract:This paper presents the assembly process using next generation electroformed stencils and Isotropic Conductive Adhesives (ICAs) as interconnection material. The utilisation of ICAs in flip-chip assembly process is investigated as an alternative to the lead and lead-free solder alloys and aims to ensure a low temperature (T < 100 °C) assembly process. The paper emphasizes and discusses in details the assembly of a flip-chip package based on copper columns bumped die and substrate with stencil printed ICA deposits at sub-100 μm pitch. A computational modelling approach is undertaken to provide comprehensive results on reliability trends of ICA joints subject to thermal cycling of the flip-chip assembly based on easy to use damage criteria and damage evaluation. Important design parameters in the package are selected and investigated using numerical modelling techniques to provide knowledge and understanding of their impact on the thermo-mechanical behaviour of the flip-chip ICA joints. Sensitivity analysis of the damage in the adhesive material is also carried out. Optimal design rules for enhanced performance and improved thermo-mechanical reliability of ICA assembled flip-chip packages are finally formulated.
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