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Design optimization of stacked layer dielectrics for minimum gate leakage currents |
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| Authors: | J Zhang J S Yuan Y Ma A S Oates |
| Affiliation: | a Chip Design and Reliability Laboratory, School of Electrical Engineering and Computer Science, University of Central Florida, P.O. Box 162450, Orlando, FL 32816 2450, USA b Bell Laboratories, Lucent Technologies, 9333 John Young Parkway, Orlando FL 32819, USA |
| Abstract: | An effective model to evaluate the leakage currents for different stacked gates deep submicron MOS transistors is presented. For a given equivalent oxide thickness of a stacked gate, the gate leakage current decreases with an increase of high-k dielectric thickness or a decrease of interlayer thickness. Turning points at high gate biases of the I–V curves are observed for Si3N4/SiO2, Ta2O5/SiO2, Ta2O5/SiO2?yNy, Ta2O5/Si3N4, and TiO2/SiO2 stacked gates except for Al2O3/SiO2 structure. Design optimization for the stacked gate architecture to obtain the minimum gate leakage current is evaluated. |
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