| 一种适用于LDO的三级误差放大器的设计 |
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| 引用本文： | 李盛林,刘桥,吴宗桂. 一种适用于LDO的三级误差放大器的设计[J]. 现代电子技术, 2010, 33(2): 15-18 |
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| 作者姓名： | 李盛林 刘桥 吴宗桂 |
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| 作者单位： | 贵州大学,理学院,贵州,贵阳,550025 |
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| 摘 要： | 为了促进LDO在低电源电压环境中的应用，提高其稳定性，在此采用SMIC0．35um，N阱CMOS工艺，设计并实现了适用于LDO内部误差放大器的一种单密勒电容频率补偿的三级CMOS运算放大器。仿真结果表明该运算放大器的工作电压范围宽（2．5～6．5V），静态电流小，开环电压增益为112．16dB，相位裕度为89．03°，增益带宽积为6．04MHz，共模抑制比为89．3dB，电源抑制比为104．8dB。
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| 关 键 词： | LDO 低压三级运放 单密勒电容 共模抑制比 电源抑制比 |
Design of Three-stage Error Amplifier for LDO |
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| LI Shenglin,LIU Qiao,WU Zonggui. Design of Three-stage Error Amplifier for LDO[J]. Modern Electronic Technique, 2010, 33(2): 15-18 |
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| Authors: | LI Shenglin LIU Qiao WU Zonggui |
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| Affiliation: | LI Shenglin,LIU Qiao,WU Zonggui(College of Science,Guizhou University,Guiyang,550025,China) |
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| Abstract: | In order to promote LDO in the low power supply voltage environment application, its stability is enhanced, using SMIC 0.35um N trap process, a three stage error amplifier with single Miller capacitor frequency compensation, which is suitable for internal error amplifier in LDO is designed and realized, simulation results indicate that this error amplifier can operate under a wide range of power supply （2. 5 - 6. 5 V）, quiescence current is small, open - loop voltage gain is about 112.16 dB, phase margin is about 89.03°, Gain - Bandwidth Product is about 6.04 MHz, common mode rejection ration is about89.3 dB, power supply rejection ration is about 104.8 dB. |
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| Keywords: | LDO |
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