Programmable switched-capacitor bump equalizer architecture |
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| Authors: | Duque-Carrillo JF Silva-Martinez J Sanchez-Sinencio E |
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| Affiliation: | Dept. of Electr. Eng., Texas A&M Univ., College Station, TX; |
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| Abstract: | A versatile and economical switched-capacitor (SC) equalizing structure to compensate attenuation characteristics is presented. The monolithic SC bump equalizer has three operational amplifiers and six capacitor banks to independently control the center frequency, bandwidth, and peak voltage gain steps for the bump (and dip) frequency response. The bump equalizer has been integrated using 3-μm CMOS (p-well) technology and occupies an area of 3.36 mm2, including an additional test amplifier and test buffer. The circuit operating from ±5-V power supplies typically dissipates 60 mW when sampled at 75 kHz |
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