| 32位双发射双流水线结构RISC微处理器设计 |
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| 引用本文： | 黄小平,樊晓桠,张盛兵,史莉雯.32位双发射双流水线结构RISC微处理器设计[J].西北工业大学学报,2011,29(1):6-11. |
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| 作者姓名： | 黄小平 樊晓桠 张盛兵 史莉雯 |
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| 作者单位： | 西北工业大学计算机学院,陕西西安,710072 |
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| 基金项目： | 国家自然科学基金(60773223,60736012); 国家863项目(2009AA01Z110); 西北工业大学科技创新基金(2008KJ02027)资助 |
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| 摘 要： | "龙腾R2"是西北工业大学自主研制的32位嵌入式RISC微处理器,与IBM公司的Power-PC750处理器pin-to-pin兼容。综合考虑面积、功耗、实时响应以及性能要求等因素,文章提出了一种应用于嵌入式处理器微架构设计的双发射双流水线结构。该结构的核心思想是在指令流水线前端处理阶段动态检测相邻指令的先后依赖关系,预先完成双发射判断。文中首先介绍了"龙腾R2"的微体系架构,然后重点讨论了基于双发射双流水结构的指令调度策略、相邻指令耦合关系、双发射下的相关处理以及精确异常考虑等。采用M ibench基准程序完成了性能评测,综合分析结果显示,该结构对算术计算类程序流加速明显,并且电路结构清晰,易于设计验证,同时发现优化存储系统结构是提升该处理器性能的关键。文章最后对"龙腾R2"的可测试性设计以及硅物理设计等关键技术进行了论述。"龙腾R2"已流片成功,整个处理器采用SMIC 180nm CMOS工艺,芯片面积5.9 mm×6.7 mm,核心频率266 MHz,CBGA360封装。
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| 关 键 词： | “龙腾R2”处理器 双发射 双流水 可测试性设计 |
Design of a 32-Bit RISC Processor with Dual-Issue and Dual-Pipeline Architecture |
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| Huang Xiaoping,Fan Xiaoya,Zhang Shengbing,Shi Liwen.Design of a 32-Bit RISC Processor with Dual-Issue and Dual-Pipeline Architecture[J].Journal of Northwestern Polytechnical University,2011,29(1):6-11. |
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| Authors: | Huang Xiaoping Fan Xiaoya Zhang Shengbing Shi Liwen |
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| Affiliation: | (Department of Computer Science and Engineering,Northwestern Ploytechnical University Xi′an 710072,China) |
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| Abstract: | A 32-bit embedded RISC processor is presented which is compatible with the PowerPC architecture.To make a balance between its area,power,performance and real-time response,a smart micro-architecture is proposed with the distinguishing feature of dual-issue and dual-pipeline.The key point of the architecture is that the instruction dispatching engine dynamically scans the data dependences between two consecutive instructions in the instruction queue and decides whether or not to perform dual-issue action in ... |
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| Keywords: | PowerPC smart micro-architecture dual-issue dual-pipeline design for test |
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