一种用于列并行ADC的改进型栅压自举开关

CMOS图像传感器中列并行模数转换器(ADC)的面积受到严格限制,ADC采样保持电路中的栅压自举开关也必须满足每列的面积要求。在传统单电容型栅压自举开关的基础上,利用源极跟随器在降低开关导通电阻的同时提高了电路的可靠性;通过体效应补偿电路降低输入变化对导通电阻的影响;同时,在列共用偏置电路上增加控制开关,减少不必要的功耗。提出的电路使用UMC 0.11μm CMOS工艺实现,电源电压为3.3V,仿真结果表明开关导通电阻降低了约28.6%,输入范围内电阻变化率小于1.2%,有效位数提高了1bit,而面积只增加了15%。流片后测试结果显示,以20MS/s的采样频率对1.97MHz的输入进行采样,测得信噪比(SNR)、无杂散动态范围(SFDR)和有效位数(ENOB)分别为85.8dB、71.1dB和11.5bit。

Design of an Improved Bootstrapped Switch for Column-parallel ADC

The area of the column-parallel ADC in CMOS image sensor was strictly limited, and the bootstrapped switch in sample and hold circuit for the ADC must also fit the area of each column. In this paper, a source follower was added to the traditional one capacitor bootstrapped switch to reduce the on-resistance and improve the reliability of the circuit. Using body effect compensation circuit to decrease the on-resistance change varies with the input. Besides, a control switch was added to the column-shared bias circuit to avoid the unnecessary power consumption. The proposed switch is implemented in UMC 0.11 μm CMOS process, the power supply is 3.3 V. Simulation results show that, the on-resistance is decreased about 28.6%, the resistance changes within 1.2% in the input range, ENOB is increased about 1 bit. However, the area is only increased 15%. The measured results after manufacturing show that the SNR, SFDR and ENOB are 85.8 dB, 71.1 dB and 11.5 bit with the input frequency of 1.97 MHz at 20 MS/s sampling rate, respectively.