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Fault modelling of ECL devices |
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| Authors: | Menon SM Jayasumona AP |
| Affiliation: | Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA; |
| Abstract: | Logic behaviour of an ECL OR/NOR gate under different physical faults is examined. It is shown that the conventional stuck-at fault modelling may be inadequate for obtaining a sufficiently high fault coverage. A new augmented stuck-at fault model is presented which provides a better coverage of physical failures.< |
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