一种用于电流舵DAC的开关顺序优化技术

提出了一种用于电流舵DAC的开关顺序优化技术。首先,将高位电流源阵列拆分成四个部分并位于四个象限中,在每个象限中采用开关顺序优化技术消除电流源阵列由PVT变化而带来的二阶梯度幅值误差；其次,对开关顺序优化后的电流源阵列根据幅值变化进行排序并重组,形成最终的电流源及开关顺序,消除了一阶梯度幅值误差和其他残余误差。与常规开关顺序优化技术相比,该技术能更有效地降低幅值误差,提高了DAC的静态性能。为了验证提出的开关顺序优化技术,基于40 nm CMOS工艺制作了一个12位200 MS/s采样频率的电流舵DAC。测试结果表明,实施开关顺序优化技术的DAC的INL、DNL分别从0.63 LSB、0.37 LSB降低到0.54 LSB、0.25 LSB。

A Switch Sequence Optimization Technology for Current Steering DAC

A switching sequence optimization technique for current steering DAC was proposed. Firstly, the MSB current source array was divided into four parts and located in the four quadrants. In each quadrant, the switching sequence optimization technology was used to eliminate the second-order amplitude error caused by the PVT change of the current source array. Secondly, the current source array with optimized switching sequence in the quadrant was sorted and reorganized according to amplitude changes to form the final current source and switching sequence, eliminating first order amplitude error and other residual errors. Compared with conventional switching sequence optimization techniques, this technique could more effectively reduce the amplitude error and improve the static performance of the DAC. To verify the proposed switching sequence optimization technique, a 12-bit 200 MS/s current steering DAC was implemented in a 40 nm CMOS process. The test results showed that through proposed switching sequence optimization technique, the INL and DNL of the DAC were reduced from 0.63 LSB and 0.37 LSB to 0.54 LSB and 0.25 LSB, respectively.