| 数字锁相环在电力系统谐波检测中的应用 |
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| 引用本文： | 王玉凤,范必双,王英健. 数字锁相环在电力系统谐波检测中的应用[J]. 电子技术应用, 2008, 34(4): 51-52 |
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| 作者姓名： | 王玉凤 范必双 王英健 |
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| 作者单位： | 长沙理工大学,电气与信息工程学院,湖南,长沙,410076;长沙理工大学,电气与信息工程学院,湖南,长沙,410076;长沙理工大学,电气与信息工程学院,湖南,长沙,410076 |
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| 摘 要： | 分析了非同步采样对谐波测量精度的影响,提出采用数字锁相环来同步被测信号的方法。数字锁相环电路采用VHDL语言和可编程逻辑器件设计实现,并用MAX+plusⅡ软件进行仿真。仿真和测试结果表明,所设计的数字锁相环可以很好地跟踪被测信号,如果模值K设为1,当跟踪至180ms时,频率误差仅为0.01Hz。
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| 关 键 词： | 数字锁相环 谐波检测 可编程逻辑器件 |
| 修稿时间： | 2007-07-21 |
The use of digital phase locked logic for harmonic measurement in power system |
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| WANG Yu Feng,FAN Bi Shuang,WANG Ying Jian. The use of digital phase locked logic for harmonic measurement in power system[J]. Application of Electronic Technique, 2008, 34(4): 51-52 |
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| Authors: | WANG Yu Feng FAN Bi Shuang WANG Ying Jian |
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| Affiliation: | WANG Yu Feng,FAN Bi Shuang,WANG Ying Jian(School of Electrical , Information Engineering,Changsha University of Science , Technology,Changsha 410076,China) |
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| Abstract: | The impact of asynchronous sampling for the accuracy of harmonic measurement is analyzed in this paper.Aiming at it,the digital phase locked Logic(DPLL) is proposed to synchronize the tested signal.The circuits of DPLL are realized with VHDL and Programmable Logic Devices(PLD) and simulated with MAX+plusⅡ.The result of simulation and test shows that the DPLL is good for tracking the tested signal with a frequency error of only 0.01Hz at 180ms when the value of K is set ‘1’. |
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| Keywords: | digital phase lock logic harmonic measurement programmable logic device |
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