On the design of random pattern testable PLA based on weighted random pattern testing

Programmable Logic Arrays (PLAs) provide a cost effective method to realize combinational logic circuits. PLAs are often not suitable for random pattern testing due to high fao-in of gates. In order to reduce the effective fan-in of gates, previous random pattern testable (RPT) PLA designs focused on partitioning inputs and product lines. In this paper we propose a new random pattern testable design of PLAs which is suitable for built-in selftest. The key idea of the proposed design is to apply weighted random patterns to the PLA under test. The proposed design method was applied to 30 example PLAs. The performance of the RPT PLAs was measured in the size of test set, area overhead, and time overhead, and compared with two other designs in test length and fault coverage. The experimental results show that the proposed design achieve short test length and high fault coverage.