Design of an ADC for subsampling video applications

This paper describes a 10 bit 30 Msample/s (MSPS) CMOS analog-to-digital converter (ADC) for high-speed signal processing, especially for subsampling applications, for example digital video broadcasting over cable (DVB-C), terrestrial (DVB-T) and handheld (DVB-H) systems. The proposed pipelined ADC shows a good figure-of-merit (FoM). It adopts a power efficient amplifier sharing technique, a symmetrical gate-bootstrapping technique with modified timing for the bottom-sampling switch of a wideband sample-and-hold (S/H) circuit, a proposed stable high-swing bias circuit for a wide-swing gain-boosting telescopic amplifier. The measured differential and integral nonlinearities of the prototype in a 0.25-μm CMOS technology show less than 0.4 least significant bit (LSB) and 0.85 LSB respectively at full sampling rate. The ADC exhibits higher than 9 effective number of bits (ENOB) for input frequencies up to about 60 MHz, which is the fourfold Nyquist rate (fs/2), at 30 MSPS. The ADC consumes 60 mW from a 3-V supply and occupies about 1.36 mm². Jian Li received the Bachelor of Engineering (B.E.) degree in electronic engineering from Xi’an Jiaotong University, Xi’an, China, in 2003. He is currently working toward the Ph.D. degree at Microelectronics department, Fudan University, Shanghai, China. His current research interest is high-speed high resolution A/D converter design. Xiaoyang Zeng was born in Hunan Province, P.R. China on April 17, 1972. He received the B.S. degree from Xiangtan University, China in 1992, and the Ph.D. degree from Changchun Institute of Optics and Fine Mechanics, Chinese Academy of Sciences in 2001. From 2001 to 2003, he worked as a post-doctor researcher at the State-Key Lab of ASIC & System, Fudan University, P.R. China. Then he joined the faculty of Department of Micro-electronics at Fudan University as an associate professor. His research interests include information security chip design, VLSI signal processing, and communication systems. Prof. Zeng is the Chair of Design-Contest of ASP-DAC 2004 and 2005, also the TPC member of several international conferences such as ASCON 2005 and A-SSCC 2006, etc. Jianyun Zhang received the B.S., M.S. and Ph.D degree in electrical engineering from Fudan University, Shanghai, China in 1997, 2000 and 2006 respectively. From 2000 to 2002, he was with Alcatel microelectronics, Belgium, where he was involved in circuit design for GSM and GPRS. In 2002, he joined Trident microsystem, where he concentrated on the design of Video AFE including data converters and mixed signal circuits. In 2005, he joined Shihong microelectronics Corp., where he is now a director of mixed signal IC for video high speed interface. His research interests include data conversion, HDMI SerDes, and analog circuit design. Lei Xie received the Bachelor of Science (B.S.) degree in microelectronics from Nankai University, Tianjin, China, in 2005. He is currently working toward the M.S. degree at Fudan University, Shanghai, China. His current research interest is high-speed high resolution A/D converter. Huan Deng received the B.S. degree in microelectronics from Fudan University, Shanghai, P.R. China, in 2003. He is currently working toward the M.S. degree in microelectronics at the State Key Lab of ASIC & System, Fudan University. He is currently involved in the design of low-power, high-speed PLL’s. Yawei Guo received the B.S. and M.S. degree in electrical engineering from Fudan University in 1999 and 2002 respectively. From 2002 to August 2003, he was with Philips Semiconductors in Shanghai. Since August 2003, he has been with Shanghai MicroScience Integrated Circuits Co., Ltd., based in Shanghai, P. R. China. He has been leading a group and developing analog and mixed signal circuits. His research interests include high-speed data communication, data converters, and phase locked loops.