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A 70-MHz 32-b microprocessor with 1.0-μm BiCMOS macrocelllibrary |
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| Authors: | Hotta T. Bandoh T. Hotta A. Nakano T. Iwamoto S. Adachi S. |
| Affiliation: | Hitachi Ltd., Ibaraki; |
| Abstract: | A custom 529 K-transistor microprocessor with a five-stage pipeline has been implemented on a 12.98-mm2 die. Employing BiCMOS macrocells, a 32-b execution unit, extensible ROM, RAM, a PLL (phase-locked loop) clock generator with bipolar drivers, and sense circuits, and a peak performance of 70 MIPS (million instructions per second) are achieved. Power consumption is 2.1 W at 40 MHz |
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