对基于DLL和PLL的射频CMOS振荡器的相位抖动比较

通过对 PL L 和 DL L 相位抖动的比较 ,结合 DL L 倍频器的结构特点 ,得出了一个有用的公式 ,这个公式可以用于在 PL L 和 DL L 两种结构中选择出一个最佳方案 ,使得在使用 CMOS工艺实现频率合成器时能够得到最佳的功耗和相位抖动的折衷 .对于倍频系数很大的倍频器宜采用基于 PL L 的结构 ,这样可以消耗较少的功率 ;而对于较小的倍频系数的倍频器要采用基于 DL L 的结构 ,这样相位抖动特性将非常优良

The Jitter Performance Comparison Between DLL and PLL-Based RF CMOS Oscillators

By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes to get an optimum jitter performance and power consumption.For a frequency synthesizer,a large multiple factor prefers PLL based configuration which consumes less power,while a small one needs DLL based topology which produces a better jitter performance.