Towards Fault-Tolerant RF Front Ends

The continuing trends of scaling have brought with them an ever-increasing array of process faults and fabrication complexities. The relentless march towards miniaturization and massive integration, in addition to increasing operating frequencies has resulted in increasing concerns about the reliability of integrated RF front-ends. Coupled with rising cost per chip, the fault-tolerant paradigm has become pertinent in the RFIC domain. Due to the high frequencies involved, traditional fault-tolerance methods used in digital and lower frequency analog circuits cannot be applied. We propose a unique methodology to achieve fault-tolerance in RF circuits through dynamic sensing and on-chip self-correction, along with the development of robust algorithms. This technique, which poses minimal overheads and is transparent during ‘normal’ use of the circuit, is demonstrated on a cascode LNA, since the LNA is critical for the performance of the entire front-end. We present simulation and fabricated results of the system designed in IBM 0.25 μm CMOS 6RF process.