H.264/AVC中CAVLC编码器的硬件设计与实现

设计了一种H.264标准的CAVLC编码器,对原有软件流程进行部分改进,提出了并行处理各编码子模块的算法结构。重点对非零系数级(level)编码模块进行优化,采用并行处理和流水线相结合的结构,减少了cavlc编码的时钟周期,提供了稳定吞吐量。采用Xilinx公司VirtexⅡ系列的xc2v250 FPGA进行实现验证,最高时钟频率可达158.1 MHz,可满足实时编码H.264高清视频要求。

Hardware design and implementation of CAVLC encoding in H.264/AVC

This paper proposes an implementation of CAVLC encoding architecture for H.264.The original software flow is im-proved.The sub-coding modules work in parallel.The emphasis is on the optimization of non-zero coefficient level coding,using parallel processing and pipelining structure to reduce the cycles of cavlc coding and provide a stable throughput.The circuit is im-plemented and verified by Virtex Ⅱxc2v250 FPGA of Xilinx.The highest frequency reached 158.1 MHz.It is sure that the design meets the real-time processing requirement for H.264 HD video encoding.