| H.264标准二进制算术编码IP核设计 |
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| 引用本文： | 陈传东,何明华,王仁平.H.264标准二进制算术编码IP核设计[J].中国集成电路,2010,19(9):59-62. |
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| 作者姓名： | 陈传东 何明华 王仁平 |
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| 作者单位： | 福州大学微电子系,福建福州350002 |
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| 基金项目： | 福建省自然科学基金重点项目，福建省新世纪优秀人才支持计划项目 |
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| 摘 要： | 设计了一款基于H.264二进制算术编码算法IP核。针对该算法硬件实现特点,对其算法结构进行特别优化,并在Verilog HDL实现过程中,以JM86源代码为模型进行功能验证。在TSMC 0.18μm工艺下,达到频率200MHz,面积0.027mm2,能够满足实际应用要求。
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| 关 键 词： | IP核二进制算术编码H.264 |
esign of Binary Arithmetic Coding IP Core for H.264 |
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| CHEN Chuan-dong,HE Ming-hua,WANG Ren-ping.esign of Binary Arithmetic Coding IP Core for H.264[J].China Integrated Circuit,2010,19(9):59-62. |
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| Authors: | CHEN Chuan-dong HE Ming-hua WANG Ren-ping |
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| Affiliation: | (Department of Microelectronics, Fuzhou University, Fuzhou, Fujian, 350002,China ) |
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| Abstract: | This paper presents the binary arithmetic coding IP core based on H.264.Depending on the characteristic of hardware accelerator, this paper presents the optimized architecture for binary arithmetic coding.The architecture is described by Verilog HDL and tested byJM86.The whole system is up to 200 MHZ frequency by adopting TSMC 0.18 μ m cell library,and is able to achieve the requirement of practical application. |
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| Keywords: | IP core binary arithmetic coding H 264 |
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