Wiring Effect Optimization in 65-nm Low-Power NMOS

This letter investigates the wiring effect on RF performance in advanced 65-nm low-power CMOS technology. New designs are proposed to minimize the parasitic resistances and capacitances associated with the interconnects in the transistor. Compared with the standard multifinger devices provided by the foundry, the device with the optimized wiring parasitic capacitances and resistances presents improvement up to $sim$ 21% for $f_{T}$ (increased from 89 to 108 GHz) and $sim$22% for $f_{max}$ (increased from 130 to 159 GHz), respectively. The extracted equivalent circuit model parameters indicate that the proposed approach can effectively minimize the parasitic effects leading to improved RF performance of the advanced MOSFETs.