| 基于WishBone总线Cache数据一致性方案 |
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| 引用本文： | 夏宏,任捷.基于WishBone总线Cache数据一致性方案[J].计算机工程与应用,2006,42(9):93-95,110. |
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| 作者姓名： | 夏宏 任捷 |
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| 作者单位： | 华北电力大学计算机系,北京,102206 |
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| 摘 要： | Cache数据一致性问题是多处理器系统中必须解决的一个难点。作者在开发LX-1164安全微处理器过程中对WishBone总线标准以及MOESI协议进行了深入研究,提出了一种基于WishBone总线的Cache数据一致性设计方案,对WishBone总线标准进行了扩充,实现了对MOESI协议支持。本设计采用SMIC公司的0.18um工艺标准单元库,经仿真测试在400MHz主频下达到设计要求。
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| 关 键 词： | WishBone Cache数据一致性 MOESI |
| 文章编号： | 1002-8331-（2006）09-0093-03 |
| 收稿时间： | 2005-09 |
| 修稿时间： | 2005-09 |
Research and Design of Cache Coherence Scheme Based on WishBone Bus |
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| Xia Hong,Ren Jie.Research and Design of Cache Coherence Scheme Based on WishBone Bus[J].Computer Engineering and Applications,2006,42(9):93-95,110. |
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| Authors: | Xia Hong Ren Jie |
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| Affiliation: | Department of Computer,North China Electric Power University,Beijing 102206 |
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| Abstract: | The cache coherence is very important in microprocessor,the author have deeply researched the which extends the WishBone standard and achieves 0.18urn technique cell of SMIC corporation,it gets the a multi-processor system.In the exploitation of LX-1164 secure WishBone and MOESI protocol,and then put forward a scheme, MOESI protocol,to solve the cache coherence.The scheme uses goal on the frequency of 400MHz. |
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| Keywords: | WishBone MOESI |
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