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Sleepy keeper style based Low Power VLSI Architecture of a Viterbi Decoder applying for the Wireless LAN Operation sustainability |
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| Authors: | Kalavathi Devi T. Priyanka E. B. Sakthivel P. Stephen Sagayaraj A. |
| Affiliation: | 1.Department of Electronics and Instrumentation Engineering, Kongu Engineering College, Perundurai, India ;2.Department of Mechatronics Engineering, Kongu Engineering College, Perundurai, India ;3.Department of Electrical and Electronics Engineering, Vellalar College of Engineering & Technology, Perundurai, India ;4.Department of Electronics and Communication Engineering, Jaishree Ram College of Engineering, Perundurai, India ; |
| Abstract: | Analog Integrated Circuits and Signal Processing - Remarkable progress in the field of wireless communication has created a research interest for Viterbi decoder with long duration of battery life,... |
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