FSM deconposition VLSI architecture for dynamically reconfiguration

While some applications in memory can be constrained by memory bandwidth and memory cost, this paper proposes a transformation of the application into a one-bit FSM. When the finite state machine is very large, one way to improve the area and delay efficiently is to break down the large finite state machine into many smaller machines. The area efficiency can be improved if fewer machines are active simultaneously in the pipelined architecture. This can be achieved when using dynamic reconfiguration to map several sub machines onto the same hardware. This paper presents a methodology to break down the large finite state machine into many smaller machines and an architecture for the dynamically reconfiguration.