| 集成电路中的多时钟域同步设计技术 |
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| 引用本文： | 赵永建,段国东,李苗.集成电路中的多时钟域同步设计技术[J].计算机工程,2008,34(9):246-247. |
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| 作者姓名： | 赵永建 段国东 李苗 |
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| 作者单位： | 1. 上海交通大学微电子学院,上海,200240;华东计算技术研究所,上海,200233
2. 华东计算技术研究所,上海,200233 |
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| 摘 要： | 针对通信过程中多时钟域之间的亚稳态现象，分析了几种同步器在集成电路异步设计中的应用。采用异步FIFO法设计ATM通信芯片中接口与内核的异步数据缓冲器。仿真验证结果表明该方法能使电路实现既定功能并提高其可靠性。
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| 关 键 词： | 亚稳态 同步器 异步FIFO 格雷码 |
| 文章编号： | 1000-3428(2008)09-0246-02 |
| 修稿时间： | 2007年7月12日 |
Synchronous Design Techniques for Multi-clock Domains in Integrated Circuit |
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| ZHAO Yong-jian,DUAN Guo-dong,LI Miao.Synchronous Design Techniques for Multi-clock Domains in Integrated Circuit[J].Computer Engineering,2008,34(9):246-247. |
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| Authors: | ZHAO Yong-jian DUAN Guo-dong LI Miao |
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| Affiliation: | (1. School of Microelectronics, Shanghai Jiaotong University, Shanghai 200240; 2. East China Institute of Computer Technology, Shanghai 200233) |
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| Abstract: | During the process of communication between different clock domains, metastability is likely to happen. This paper discusses several applications of different synchronizers in IC asynchronous design. Asynchronous FIFO is applied to the design of asynchronous data buffer between the interface and the core of ATM communication chip. The results of simulation show that the method can increase the reliability as well as realize the desired function. |
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| Keywords: | metastability synchronizer asynchronous FIFO Gray code |
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