A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique |
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| Authors: | Okaniwa Y. Tamura H. Kibune M. Yamazaki D. Tsz-Shing Cheung Ogawa J. Tzartzanis N. Walker W.W. Kuroda T. |
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| Affiliation: | Dept. of Electron. & Electr. Eng., Keio Univ., Kanagawa, Japan; |
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| Abstract: | A differential comparator that can sample 40-Gb/s signals and that operates off a single 1.2-V supply was designed and fabricated in 0.11-/spl mu/m standard CMOS technology. It consists of a front-end sampler, a regenerative stage, and a clocked amplifier to provide a small aperture time and a high toggle rate. The clocked amplifier employs a bandwidth modulation technique that switches the feedback gain to reduce the reset time while keeping the effective gain high. We confirmed that the comparator receives a 40-Gb/s data stream at a toggle rate of 10 GHz with bit error rate less than 10/sup -12/ by laboratory measurements. |
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