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Reliability aspects of gate oxide under ESD pulse stress
Authors:Adrien Ille  Wolfgang Stadler  Harald Gossner  Kai Esmark  David Alvarez  Robert Gauthier
Affiliation:a Infineon Technologies, D-81726 Munich, Germany
b Laboratoire Matériaux et Microélectronique de Provence (L2MP), UMR CNRS 6137, Université de Provence, ISEN, Maison des technologies, Place G. Pompidou, 83000 Toulon, France
c IBM Semiconductor R&D Center, System and Technology Group, Essex Junction, VT 05452, USA
Abstract:Power law time-to-breakdown voltage acceleration is investigated down to ultra-thin oxides (1.1 nm) in the ESD regime in inversion and accumulation. Breakdown modes, oxide degradation and device drifts under ESD-like stress are discussed as function of the oxide thickness. The consequent impacts on the ESD design window are presented.
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