80 Gbit/s PAM4光接收机低噪声模拟前端电路设计

采用UMC 28 nm CMOS工艺,设计了一款应用于光接收机、工作在80 Gbit/s PAM4的低噪声模拟前端电路(AFE)。对噪声和带宽进行折中设计,采用了跨阻放大器(TIA)级联连续时间线性均衡器(CTLE)技术和输入电感峰化技术。为了更好地控制低频增益,进一步拓展带宽,采用了跨导跨阻(gm-TIA)结构的VGA。在输入电容100 fF和供电电压1.2 V下,实现的跨阻增益为48.5 dBΩ,带宽为36.1 GHz,平均等效输入噪声电流为22.6 pA/Hz,功耗为14.5 mW。

Low-Noise Analog Front-End Circuit Design for 80 Gbit/s PAM4 Signal Optical Receiver

A low-noise analog front-end circuit (AFE) was designed using UMC 28 nm CMOS technology for optical receivers operating at 80 Gbit/s PAM4. To address the tradeoff between the noise and bandwidth, we adopted a trans-impedance amplifier (TIA) cascaded continuous time linear equalizer (CTLE) and input inductor peaking. A VGA with trans-conductance and a trans-impedance (gm-TIA) structure was adopted to effectively control the low-frequency gain and further expand the bandwidth. The circuit achieves a trans-impedance gain of 48.5 dBΩ, a bandwidth of 36.1 GHz, an average equivalent input current noise of 22.6 pA/Hz, and a power consumption of 14.5 mW, under the conditions of an input capacitance of 100 fF and a supply voltage of 1.2 V.