一种6倍无源增益低OSR低功耗的二阶NS SAR ADC

针对一阶噪声整形(NS)往往需要增加功耗而以较高的过采样比(OSR)来实现较高的有效位数(ENOB),提出了一种低OSR、低功耗的二阶无源NS SAR ADC。该无源NS模块较高的无源增益可以更好地抑制比较器的噪声；其残差电压是通过开关MOS阵列复用积分电容实现采样,从而无需额外的残差采样电容,避免了残差采样电容清零和残差采样时kT/C噪声的产生,因此减小了总的kT/C噪声。180 nm CMOS工艺仿真结果表明,在不使用数字校准的情况下,所设计的10位二阶无源NS SAR ADC电路以100 kS/s的采样率和5的OSR,实现了13.5位ENOB,电路功耗仅为6.98 μW。

Second-Order NS SAR ADC with Six-Fold Passive Gain, Low OSR, and Low Power Consumption

Aiming at first-order noise shaping (NS), which often compromises power consumption to achieve a high effective number of bits (ENOB) and oversampling rate (OSR), this study proposes a second-order passive NS SAR ADC with a low OSR and low power consumption, whose higher passive gain can better suppress the noise of the comparator, and the residual voltage is achieved by multiplexing the integrating capacitors through the switching MOS array. Thus, the generation of the residual sampling capacitance clearing and residual sampling kT/C noise is avoided, reducing the total kT/C noise. Based on a 180 nm CMOS process, the simulation results show that without digital calibration, the designed 10-bit second-order passive NS SAR ADC circuit achieves an ENOB of 13.5 bits at a sampling rate of 100 kS/s with an OSR of 5. The power consumption is 6.98 μW.