| 一种高性能数字下变频硬件计算结构 |
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| 引用本文： | 王超,谢憬,封成冬.一种高性能数字下变频硬件计算结构[J].黑龙江电子技术,2014(7):94-97. |
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| 作者姓名： | 王超 谢憬 封成冬 |
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| 作者单位： | 上海交通大学微电子学院,上海200030 |
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| 摘 要： | 数字下变频是软件无线电的核心技术，随着通信技术的发展，如今对其处理速度要求越来越高。现提出了一种高性能的数字下变频硬件计算结构，使用CORDIC，流水线划分，重定时等技术来优化数字下变频各个模块的硬件结构。通过和传统设计方案的实验比较，证明了本方案能在将FPGA总体资源使用等效门数减少29．54％的情况下，将最高数据吞吐率提升6．74倍。
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| 关 键 词： | 数字下变频 结构优化 流水线 重定时 |
High performance digital down converter structure |
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| Authors: | WANG Chao XIE Jing FENG Cheng-dong |
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| Affiliation: | ( Scheol of Microelectronics, Shanghai Jiaotong University, Shanghai 200030, China) |
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| Abstract: | Digital down converter （DDC） is the core technology of software radio. As the development ofwireless communication, there is a growing demand in the calculate speed of DDC. This paper presents ahigh performance DDC hardware structure. CORDIC, pipelining, retiming are used to optimize eachhardware unit in it. The experiment results show that in comparison with the traditional DDC structure,the optimized DDC can reduce FPGA design equivalent gate count by 29.54% and increase the maximumdata throughput by 6.74 times. |
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| Keywords: | digital down converter structure optimization pipeline retiming |
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