A Double Sampling 8-Bit, 50 MS/s, 32 mW Pipeline Converter with +6 dB Overdrive Headroom

An 8-bit, 50 MS/s pipeline converter is presented with peak SNR and SFDR of 43.1 dB and 52.5 dB, corresponding to effective number of bits of 6.9. The circuit is implemented in a 0.35 m CMOS process, the core area is 0.36 mm² and its analog and digital current consumptions (including I/O buffers) are 6.2 mA and 4.5 mA from a 3 V supply. The low power consumption is achieved by using two banks of sampling capacitors (double sampling) and a mixed architecture giving 1+1+1+2+3 bits per stage. The mixed architecture means that a full ninth bit cannot be coded, but instead it is a employed as an almost 6 dB overdrive input range. The maximum allowable comparator errors in different architectures are calculated and the benefits of excess redundancy are discussed.