| 小波滤波器低功耗并行的VLSI结构设计 |
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| 引用本文： | 兰旭光,郑南宁,薛建儒,王飞,刘跃虎. 小波滤波器低功耗并行的VLSI结构设计[J]. 计算机研究与发展, 2005, 42(11): 1889-1895 |
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| 作者姓名： | 兰旭光 郑南宁 薛建儒 王飞 刘跃虎 |
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| 作者单位： | 西安交通大学人工智能与机器人研究所,西安,710049;西安交通大学人工智能与机器人研究所,西安,710049;西安交通大学人工智能与机器人研究所,西安,710049;西安交通大学人工智能与机器人研究所,西安,710049;西安交通大学人工智能与机器人研究所,西安,710049 |
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| 基金项目： | 国家“八六三”高技术研究发展计划基金项目(2002AA103011)，国家自然科学基金项目(60021302,60205001,60405004)，西安交通大学“十五”211“智能信息处理技术与信息科学计算方法”建设项目~~ |
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| 摘 要： | 提出一种基于行和提升算法,实现JPEG2000编码系统中的小波正反变换(discretewavelettransform)的低功耗、并行的VLSI结构设计方法·利用该方法所得结构一次处理两行数据,分时复用行处理器,使行处理器内以及行、列处理器实现并行处理,且最小化行缓存·对称扩展通过嵌入式电路实现,整个结构采用流水线设计方法优化,加快了变换速度,增加了硬件资源利用率,降低了功耗,效率几乎达到100%·小波滤波器正反变换结构已经经过FPGA验证,可作为单独的IP核应用于正在开发的JPEG2000图像编解码芯片中·
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| 关 键 词： | 二维离散小波变换 VLSI JPEG2000 并行结构 提升方法 基于行 |
| 收稿时间： | 2004-05-17 |
| 修稿时间： | 2004-05-172005-01-27 |
Low-Power and High-Speed VLSI Architecture Design of 2-D DWT/IDWT |
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| Lan Xuguang,Zheng Nanning,Xue Jianru,Wang Fei,Liu Yuehu. Low-Power and High-Speed VLSI Architecture Design of 2-D DWT/IDWT[J]. Journal of Computer Research and Development, 2005, 42(11): 1889-1895 |
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| Authors: | Lan Xuguang Zheng Nanning Xue Jianru Wang Fei Liu Yuehu |
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| Abstract: | A low-power, high-speed and minimum-area architecture which performs two-dimension discrete wavelet transform (2-D DWT) of JPEG2000 is proposed by using a line-based and lifting scheme. The architecture consists of one row processor and one column processor. The row processor, which is time-multiplexed, computes in parallel with the column processor, and two pixels can be encoded in one clock cycle. The extensions at the boundaries are implemented by an embedded circuit, and the memory is minimized. The whole architecture, which is optimized in pipelined way to speed up and achieve higher hardware utilization, has been implemented in FPGA, and can be used as a compact and independent IP core for JPEG2000 VLSI implementation. |
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| Keywords: | 2D discrete wavelet transform VLSI JPEG2000 parallel architecture lifting schemes line-based |
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