Three level partitioning algorithm for circuit simulation on multiprocessor

Circuit partitioning issues for circuit simulation on distributed multiprocessors are discussed in this paper. An efficient three-level partitioning algorithm for large-scale circuit is proposed. Using this algorithm, we can partition a large-scale circuit into r subcircuits of similar size while keeping the interconnect set of nodes to a minimum. This algorithm can be implemented for parallel processing. Some examples are given to show the performance of the algorithm.