| 基于单片机和EDA技术的逻辑分析仪设计 |
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| 引用本文： | 夏新恩,洪远泉.基于单片机和EDA技术的逻辑分析仪设计[J].计算机工程,2005,31(16):207-209,221. |
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| 作者姓名： | 夏新恩 洪远泉 |
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| 作者单位： | 1. 韶关学院计算机科学系,韶关512005
2. 韶关学院实验中心,韶关,512005 |
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| 摘 要： | 采用单片机控制8路逻辑信号电平采集；采用EDA技术设计的CPLD芯片处理逻辑信号，控制点阵扫描和分析结果在示波器上显示；单片机和CPLD间采用中断方式交换数据。该设计具有1、3级触发方式，触发字位置和浮动时标线显示等功能。
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| 关 键 词： | 点阵扫描控制 逻辑分析 CPLD VHDL编程 |
| 文章编号： | 1000-3428（2005）16-0207-03 |
| 收稿时间： | 2004-06-07 |
| 修稿时间： | 2004-06-07 |
Design of Logical Analysis Apparatus Based on One-chip Microcomputer and EDA's Technology |
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| XIA Xinen,HONG Yuanquan.Design of Logical Analysis Apparatus Based on One-chip Microcomputer and EDA''''s Technology[J].Computer Engineering,2005,31(16):207-209,221. |
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| Authors: | XIA Xinen HONG Yuanquan |
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| Abstract: | This design uses the one-chip microcomputer to be controlled gathering of logical signal levels of 8 tunnels, uses CPLD's chip of EDA'stechnical design to the logic signal processing and control scanning to the lattice signal and the result of display analysis on the oscillograph , usesthe interrupt mode exchange data between one-chip microcomputer and CPLD. This design has 1 and 3 grade of method of activation, trigger wordseat display and time to be marked thread display etc. merit ability. |
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| Keywords: | Lattice scanning control Logical analysis CPLD VHDL's programming |
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