A parity-preserving multi-input signature analyzer and its application for concurrent checking and BIST |
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Authors: | Michael Goessel Egor S Sogomonyan |
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Affiliation: | (1) Max-Planck-Society, Fault-Tolerant Computing Group at the University of Potsdam, PSF 601553, 14415 Potsdam, Germany;(2) Institute of Control Sciences, Russian Academy of Sciences, Profsouznaya ul. 65, 117806 Moscow, Russia |
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Abstract: | In this paper a joint implementation of a parity preserving multi-input signature analyzer (PMISA) and a parity checker is
described. The PMISA simultaneously can be used for concurrent checking and for testing of digital circuits. In the case of
concurrent checking errors are detected by their erroneous parity. If a circuit is tested errors are detected either by their
erroneous parity or by the erroneous signature of the PMISA. A possible scan-mode of the PMISA allows its application in a
scan path with parity-encoded inputs and outputs of the combinational modules which are driven by register sets. In normal
operation mode all the registers of the PMISA can be utilized as functional registers of the combinational circuit. |
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Keywords: | concurrent error detection on-line testing built-in-self-test parity-preserving signature analyzer |
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