Decoded-source sense amplifier for high-density DRAMs |
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| Authors: | Okamura J-I Okada Y Koyanagi M Takeuchi Y Yamada M Sakurai K Imada S Saito S |
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| Affiliation: | Toshiba Corp., Kawasaki; |
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| Abstract: | The decoded-source sense amplifier (DSSA) for high-speed, high-density DRAMs is discussed. To prevent clamping of the common-source node of the sense amplifier caused by bit-line discharge current, the DSSA has an additional latching transistor with a gate controlled by a column decoder. The DSSA has been successfully installed in a 4-Mb DRAM and provided a RAS access time of 60 ns under a Vcc of 4 V at 85°C |
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