分组密码处理器的可重构分簇式架构

该文在研究分组密码算法处理特征的基础上，提出了可重构分簇式分组密码处理器架构。在指令的控制下，数据通路可动态地重构为4个32bit簇，2个64bit簇和一个128bit簇，满足了分组密码算法数据处理所需的灵活性。基于分簇结构，提出了由指令显性地分隔电路结构的低功耗优化技术，采用此技术使得整体功耗降低了36.1%。设计并实现了5级流水线以及运算单元内流水结构，处理AES/DES/IDEA算法的速度分别达到了689.6Mbit/s, 400Mbit/s和416.7Mbit/s。

Reconfigurable Clustered Architecture of Block Cipher Processor

This paper presents the reconfigurable clustered architecture of block cipher processor. Appointed by instructions, the data-path of this architecture can be dynamically configured to be three modes, which includes 4clusters, 2clusters and single cluster mode. In different mode, different operations can be done, which improves the flexibility of this processor. Basing on clustered architecture, Explicit-decomposition low-power-design method is presented, which can reduce the power by 36.1%. With 5stages pipeline and wave-pipeline, this processor can work in a high rate. And the performances of AES/DES/IDEA reach 689.6Mbit/s, 400Mbit/s, 416.7Mbit/s.