并行采集系统触发晃动实时校正技术研究

在并行实时采集系统,大量的采用了并行时间交替采样和数据分相存储技术,但采样数据的并行存储将引起触发抖动问题,严重降低了整个系统的性能。在分析触发抖动原因的基础上,提出了采用时间内插计数法,通过实时放大并测量触发信号和并行采样时钟的时间间隔,对触发晃动进行校正,从而达到降低触发抖动,提高波形显示稳定性的目的,并结合工程应用,在采用8路拼合的2GSPS实时采样数字存储示波器中实现了对触发晃动的校正,最后给出了该功能的性能测试结果。

Research on the real-time calibration technology of trigger jitter in the parallel sampling systems

The parallel time-interleaved ADC and parallel storage is used widely in the parallel sampling systems, but these technologies lead to trigger jitter and degrades the overall performance of system. After analysing the cause of trigger jitter, this paper proposed a method based on time interpolator, through the real-time measurement trigger signal and sampling clock time interval, the trigger jitter is calibrated to achieve the lower trigger jitter and improve the stability of the purpose of waveform display...