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三层金属布线的SOG隔离工艺开发
引用本文:彭力,赵文彬,王国章,于宗光. 三层金属布线的SOG隔离工艺开发[J]. 半导体学报, 2010, 31(12): 126003-3
作者姓名:彭力  赵文彬  王国章  于宗光
基金项目:国家重点基础研究规划项目
摘    要:摘要: SOG平坦化技术是一种采用液态介质材料填充CMOS后段布线工艺中金属间隙的工艺技术,它使得硅片表面平坦化,物理特性上它和PECVD淀积SiO2类似,二者具有相似的电特性,SOG材料的介电常数低,具有良好的绝缘特性,是一种常用的金属层间隔离材料。但SOG材料和金属间的粘附性差、容易开裂等问题都阻碍了SOG技术作为多层金属层间介质的应用,特别是在大生产工艺上。本文采用首先CVD淀积一层薄SiO2,接着进行SOG涂敷固化和反腐工艺,最后再淀积顶层SiO2,形成三明治介质机构,这样有利于提高粘附性、防止开裂和孔中毒等问题,同时用电扫描显微镜对采用此结构的三层布线工艺进行纵向剖面分析。这种结构在CMOS三层布线工艺中已成功开发,并在0.5m CMOS DPTM批量生产中得到应用和验证。

关 键 词:金属互连  金属工艺  自旋玻璃  SiO2薄膜  扫描电镜分析  PECVD  大学实验室  绝缘材料
修稿时间:2010-08-11

Development of spin-on-glass process for triple metal interconnects
Peng Li,Zhao Wenbin,Wang Guozhang and Yu Zongguang. Development of spin-on-glass process for triple metal interconnects[J]. Chinese Journal of Semiconductors, 2010, 31(12): 126003-3
Authors:Peng Li  Zhao Wenbin  Wang Guozhang  Yu Zongguang
Affiliation:No. 58 Institute, China Electronic Technology Group Corporation, Wuxi 214035, China;No. 58 Institute, China Electronic Technology Group Corporation, Wuxi 214035, China;No. 58 Institute, China Electronic Technology Group Corporation, Wuxi 214035, China;No. 58 Institute, China Electronic Technology Group Corporation, Wuxi 214035, China
Abstract:Spin-on-glass (SOG), an interlayer dielectric material applied in liquid form to fill narrow gaps in the sub-dielectric surface and thus conducive to planarization, is an alternative to silicon dioxide (SiO2) deposited using PECVD processes. However, its inability to adhere to metal and problems such as cracking prevent the easy application of SOG technology to provide an interlayer dielectric in multilevel metal interconnect circuits, particularly in university processing labs. This paper will show that a thin layer of CVD SiO2 and a curing temperature below the sintering temperature of the metal interconnect layer will promote adhesion, reduce gaps, and prevent cracking. Electron scanning microscope analysis has been used to demonstrate the success of the improved technique. This optimized process has been used in batches of double-poly, triple-metal CMOS wafer fabrication to date.
Keywords:SOG  etch-back  planarization  multilevel metal interconnect
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