2.7 V 50 MHz IF sampling ΔΣ modulator with +37 dBV IIP3

The design and experimental results of a 2.7 V 50 MHz switched-capacitor DS modulator in a 0.35 μm BiCMOS process are presented. The circuit is targeted for the IF section of a radio receiver in a GSM cellular phone. It combines frequency downconversion with analogue to digital conversion by directly sampling an input signal from an IF of 50 MHz. The measured peak signal-to-noise ratio for a 100 kHz bandwidth is 81 dB with a 53 MHz blocking signal and the measured IIP3 for IF input is +36.9 dBV