面向高层次综合的自定义指令自动识别方法

针对在高层次综合（HLS）过程中性能提升、功耗降低困难等问题，提出了一种面向高层次综合的自定义指令自动识别方法。在高层次综合过程之前实现对自定义指令的枚举和选择，从而为高层次综合提供通用的自定义指令识别方法。首先，将高层次源代码转换为控制数据流图（CDFG），实现了对源代码的预处理；其次，基于控制数据流图内的数据流图（DFG），采用子图枚举算法以自底而上的方式枚举出所有连通凸子图，有效提高了用户可灵活修改约束条件的能力；然后，分别从面积、性能和代码量三个角度考虑，利用子图选择算法选择部分最佳子图作为最终的自定义指令；最后，用所选的自定义指令重新生成新代码作为高层次综合工具的输入。与传统高层次综合相比，采用基于出现频率的模式选择可平均减少19.1%的面积，采用基于关键路径的子图选择可平均减少22.3%的时延。此外，与TD算法相比，所提算法的枚举效率平均提升70.8%。实验结果表明，自定义指令自动识别方法使高层次综合在电路设计中能够显著地提升性能，减少面积和代码量。

Automatic custom instructions identification method for high level synthesis

Aiming at the problems that it is difficult to improve performance and reduce power consumption in the process of High Level Synthesis (HLS), an automatic custom instructions identification method for high level synthesis was proposed. The enumeration and selection of custom instructions were implemented before high level synthesis, so as to provide a universal automatic custom instructions identification method for high level synthesis. Firstly, the high level source code was transformed into a Control Data Flow Graph (CDFG), and the source code was preprocessed. Secondly, a subgraph enumeration algorithm was used to enumerate all the connected convex subgraphs in a bottom-up manner from the Data Flow Graph (DFG) based on control data flow graph, which effectively improved the user's ability to flexibly modify the constraints. Then, considering the area, performance and code size, the subgraph selection algorithms were used to select partial optimal subgraphs as the final custom instructions. Finally, a new code was regenerated by incorporating the selected custom instructions as the input of high level synthesis. Compared with the traditional high level synthesis, the pattern selection based on frequency of occurrence reduced the area by an average of 19.1%. Meanwhile, the subgraph selection based on critical paths reduced the latency by an average of 22.3%. In addition, compared with Transitive Digraph (TD) algorithm, the enumeration efficiency of the proposed algorithm was increased by an average of 70.8%. The experimental results show that the automatic custom instructions identification method can significantly improve performance and reduce area and code size for high level synthesis in circuit design.