面向系统级芯片的串行外设接口模块设计

针对传统串行外设接口(SPI)模块设计不灵活、不利于扩展、不支持乱序访问的缺陷,设计了一种面向系统级芯片(SoC)的SPI模块。首先,根据SPI通信协议,设计SPI基本架构;其次,根据SPI架构,设计相应输入输出状态机(FSM)、扩展端口及支持乱序访问的标识(ID)模块;再次,利用Synopsys公司的Verilog模拟器编译(VCS)仿真工具对该SPI设计的正确性进行验证;最后,为该SPI设计搭建参数可配置的随机验证环境,对代码覆盖率报告进行分析,并有针对性地手动加入测试点提高各项代码覆盖率。仿真结果表明,与传统的SPI设计相比,面向SoC的SPI模块设计支持高级可扩展接口(AXI)总线扩展,具有8个独立的读写通道,各通道间支持可乱序访问,不会出现通道堵塞情况。

Design of serial peripheral interface module for system-on-chip

The traditional module design for Serial Peripheral Interface (SPI) is inflexible, unfavorable to expand and does not support the out-of-order access. In order to solve the problems, a kind of SPI module for System-on-a-Chip (SoC) was designed. Firstly, the basic architecture of SPI was designed according to the SPI communication protocol. Secondly, the Finite State Machine (FSM) of input and output, the extension ports and the Identification (ID) module supporting the out-of-order access were designed according to the architecture of SPI. Thirdly, the correctness of the SPI design was verified by using Verilog Compile Simulator (VCS) simulation tool of Synopsys. Finally, a random verification environment was built for the SPI design, in which parameters could be configured. The code coverage report was analyzed and test points were manually added to improve the code coverage rate. The simulation results show that, compared with the traditional design of SPI, the design of SPI module for SoC supports Advanced eXtensible Interface (AXI) bus extension and has eight independent read and write channels, each of which can be out-of-order accessed. The proposed design is incapable of occurring channel congestion.