DDR SDRAM与FPGA的高速接口设计

双倍数据率同步动态随机存储器(DDR SDRAM)以其大容量、高速率和良好的兼容性在许多领域得到了相当广泛的应用。本文对DDR SDRAM的工作原理、控制器的结构、接口和时序进行了介绍和分析。利用IP核设计了存储控制器,实现了DDR SDRAM与FPGA的高速接口。通过软件仿真和硬件实验测试,证明了本设计的正确性和可行性。

Design of the high-speed interface between DDR SDRAM and FPGA

The DDR (Double Data Rate) SDRAM has many advantages and has been used in many fields because of its large capacity and high speed operation.The operation theory,structure of memory controller,interface and timing are introduced and analyzed in this article.The high-speed interface between DDR SDRAM and FPGA are implemented via Altera IPcore.This design is proved to be valid and feasible by software simulation and hardware system operation.