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A Prototype of the Read-out Subsystem of the BESIII DAQ Based on PowerPC
作者姓名:陶宁  初元萍  金革  赵京伟
作者单位:[1]Department of Modern Physics, University of Science and Technology of China, Hefei230026, China [2]Institute of High Energy Physics, Chinese Academy of Sciences, Beijing 100049, China
基金项目:The project supported by Beijing Electron Positron Collider (BEPCII) Upgrade Project
摘    要:1 Overview of the data acquisi-tion system for BES IIIAfter having run successfully for more than tenyears, the BEPC e+ e- collider will be upgradedfor higher luminosity, which will be increased to1033 cm-2 ·sec-1 1]. Therefore, its detector BESII willbe upgraded to BESIII in order to take advantage ofthis increased luminosity, named BESIII.Trigger rate and event size define the performance re-quirements for the data acquisition (DAQ) system. Forpeak luminosity, we expect a L1 t…

关 键 词:读出器  计算机控制  DMA转移  数据管理
收稿时间:2005-01-11
修稿时间:2005-01-11

A Prototype of the Read-out Subsystem of the BESIII DAQ Based on PowerPC
Tao Ning, Chu Yuanping,Jin Ge, Zhao Jingwei.A Prototype of the Read-out Subsystem of the BESIII DAQ Based on PowerPC[J].Plasma Science & Technology,2005,7(5):3065-3068.
Authors:Tao Ning  Chu Yuanping  Jin Ge  Zhao Jingwei
Affiliation:1. Department of Modern Physics, University of Science and Technology of China, Hefei 230026, China;2. Institute of High Energy Physics, Chinese Academy of Sciences, Beijing 100049, China
Abstract:This article describes the prototype of the read-out subsystem which will be subject to the BESIII data acquisition system. According to the purpose of the BESIII, the event rate will be about 4000 Hz and the data rate up to 50 Mbytes/sec after Level 1 trigger. The read-out subsystem consists of some read-out crates and a read-out computer whose function is to initialize the hardware, to collect the event data from the front-end electronics after Level 1 trigger, to transfer data fragments to the computer in online form through two levels of computer pre-processing and high-speed network transmission. In this model, the crate level read-out implementation is based on the commercial single board computer MVME5100 running the VxWorks operating system. The article outlines the structure of the crate level testing platform of hardware and software. It puts emphasis on the framework of the read-out test model, data process flow and test method at crate level. Especially, it enumerates the key technologies in the process of design and analyses the test results. In addition, results which summarize the performance of the single board computer from the data transferring aspects will be presented.
Keywords:BESIII DAQ  readout system  single board computer  VMEbus  DMA transfer
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