首页 | 本学科首页   官方微博 | 高级检索  
     


A wide supply voltage range and low-power all-digital clock generator
Authors:Kuo-Hsing Cheng  Jen-Chieh Liu  Hong-Yi Huang  Yu-Tso Chen
Affiliation:1. Department of Electrical Engineering, National Central University, Jhongli, Taiwan
2. Information and Communications Research Laboratories, Industrial Technology Research Institute, Hsinchu, Taiwan
3. Graduate Institute of Electrical Engineering, National Taipei University, New Taipei, Taiwan
Abstract:This study presents a low-power all-digital clock generator (ADCG) for a wide supply voltage range system. The proposed ADCG limits the maximum supply current to 100 μA at a supply voltage ranging from 1.6 to 3.6 V. The ADCG also uses a digitally controlled oscillator (DCO) to extend its operational frequency range. The proposed DCO controls the supply current and divider circuits for a wide supply voltage range. The output duty cycle of ADCG falls within 50 ± 1.9 % using a duty cycle corrector. The maximum peak-to-peak jitter is less than 2.7 % at 8.38 MHz for a digital water meter application (DWM). The operational frequencies of 1.45 and 8.38 MHz at 1.8 V are 3.1 and 36.7 μA, respectively. The core area of ADCG is 0.14 mm2 for a 0.35 μm CMOS process. The operational frequency of ADCG ranges from 4.5 to 9.2 MHz at a supply voltage ranging from 1.6 to 3.6 V. This clock generator can also be applied to microcontroller applications.
Keywords:
本文献已被 SpringerLink 等数据库收录!
设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司  京ICP备09084417号